FIG. 9 illustrates large capacitance signal lines, such as an internal bus line 102 or a clock line 103, in an LSI (Large Scale Integrated circuit) 101.
For example, the LSI 101 is provided therein with a table memory 111, data memories 112 and 113, an instruction memory 114, an ALU (Arithmetic and Logic Unit) 115, a multiplier 116, a sequencer 117, a clock driver 118, and a random logic 119. These sections transmit or receive data, an address, a control signal, or the like via the internal bus line 102 including a data bus, an address bus, a peripheral bus, or the like. Further, to each of these sections, a clock (clock signal) is supplied from the clock driver 118 via the clock line 103.
In order to realize a high performance of the LSI 101, it is essential to (I) realize an ultra high-speed clock transmission in the clock line 103, (II) realize a high-speed signal transmission in the internal bus line 102, and (III) increase a number of lines extending side by side, in the internal bus line 102. However, an increasing power consumption accompanying electric charging/discharging to/from these large capacitance lines has been a significant concern.
In many cases, an inverter circuit is used as a typical driver circuit. This inverter circuit however is a main cause of the increase in an overall power consumption of the LSI 101. This is because the use of the inverter circuit causes a signal level to swing up to a level of a power source voltage.
In view of the foregoing problem, a large number of methods have been suggested in which the power consumption is reduced by reducing the amplitude of the signal in the bus line. However, these methods are hardly used, on the grounds that variations in a process of manufacturing the LSI 101 and changes in an operating environment cause significant changes in properties of the LSI 101 and unstable operation of the LSI 101.
For example, a reduced-amplitude circuit for reducing the power consumption is disclosed in Atsuki Inoue et al., “A Low Power SOI Adder Using Reduced-Swing Charge Recycling Circuits”, ISSCC 2001, Feb. 7, 2001. The following describes in detail about a typical reduced-amplitude bus driving method disclosed in the document.
FIG. 10 illustrates a basic configuration of a typical conventional reduced-amplitude bus driving system. Each of FIG. 11(a) through FIG. 11(c) indicates an amplitude of a signal in each section of the small amplitude bus driving system.
In the bus driving system illustrated in FIG. 10, signals are transmitted from a driver-side device 121 to a receiver-side device 122 via a large capacitance bus line 123 having signal lines L1 and L2. As illustrated in FIG. 11(a) and FIG. 11(c), High levels of pre-transmission signals (TX signals) from the driver-side device 121 and received signals (RX signals) received by the receiver-side device 122 are set at a power source voltage VDD, and Low levels of the TX signals and the RX signals are set at a ground potential GND.
Driver circuits 125 and 126 respectively convert (I) a pre-transmission signal and (II) a pre-transmission signal that has been inverted by an inverter 124 into a signal whose High level voltage is lower than the power source voltage VDD, and whose Low level voltage is higher than the ground potential GND. Accordingly, as illustrated in FIG. 11(b), in the bus line 123, the signal levels of the transmission signals are restrained from fully swinging between the power source voltage VDD and the ground potential GND. Since the power consumption is proportional to the amplitude, power consumed in the bus line 123 is reduced by reducing the amplitudes of the transmission signals. Further, the received signals are reconverted by a differential amplifier 127 in the receiver-side device 122, so that signal levels of the received signals fully swing between the power source voltage VDD and the ground potential GND.
FIG. 12(a) illustrates a specific example of the reduced-amplitude bus driving circuit in the reduced-amplitude bus driving system illustrated in FIG. 10, and FIG. 12(b) illustrates an output signal from the reduced-amplitude bus driving circuit. FIG. 13(a) illustrates another specific example of the reduced-amplitude bus driving circuit in the reduced-amplitude bus driving system illustrated in FIG. 10, and FIG. 13(b) illustrates an output signal from the reduced-amplitude bus driving circuit.
The bus driving circuit illustrated in FIG. 12(a) is a Vtn-down type circuit. This bus driving circuit is a driver circuit for generating two output signals S1 and S2 which are complementary with respect to each other. Such bus driving circuit has (I) nMOS transistors N1 and N2 being serially connected, the nMOS transistors N1 and N2 being provided between a power line and a ground line, and (II) nMOS transistors N3 and N4 being serially connected with each other, the nMOS transistors N3 and N4 being provided between a power line and a ground line. Signals are inputted as they are to gates of the nMOS transistors N1 and N4, and signals being inverted by the inverters 131 and 132 are respectively inputted to gates of the nMOS transistors N2 and N3.
As illustrated in FIG. 12(b), in the bus driving circuit, the respective Low level voltages of the output signals S1 and S2 are equal to the ground potential GND. However, when signal levels of the output signals S1 and S2 approach the High level voltages, the transistors turn off at a point where respective gate-source voltages of the nMOS transistors N1 and N3 reach a threshold voltage Vtn of the nMOS transistors N1 and N3. Accordingly, the High level voltages of the output signals S1 and S2 are lower, by the threshold voltage Vtn, than the power source voltage VDD.
The bus driving circuit illustrated in FIG. 13(a) is a diode-type circuit. This bus driving circuit includes a control circuit 141 and a driver circuit 142 being controlled by the control circuit 141. Further, in order to generate two output signals S1 and S2 which are complementary with respect to each other, the driver circuit 142 has: (I) pMOS transistors TP1 and TP2, and nMOS transistors TN1 and TN2, each of which serves as a driver transistor; and (II) switches SW1 and SW2.
The pMOS transistor TP1 and the nMOS transistor TN1 are serially connected with each other, and are provided between a power line and a ground line. Further, the pMOS transistor TP2 and the nMOS transistor TN2 are serially connected with each other, and are provided between a power line and a ground line. Gates of the pMOS transistor TP1 and the nMOS transistor TN1 are connected, via the switches SW1, to VDD/GND or an output line (S1 line) for the output signal S1. Further, gates of the PMOS transistor TP2 and the nMOS transistor TN2 are connected, via the switches SW2, to VDD/GND or an output line (S2 line) for the output signal S2.
The control circuit 141 controls the switches SW1 and SW2 so as to switch-over signal lines in accordance with a signal level of input data, the signal lines respectively being connected with each of the foregoing gates in the driver circuit 142. FIG. 13(a) illustrates a case in which the signal level of the input data is High.
The connections of the driver transistors are controlled as follows, in accordance with the signal levels of the input data.
(1) When the Signal Level of the Input Data is High.
The gate of the pMOS transistor TP1 is connected to the S1 line.
The gate of the nMOS transistor TN1 is connected to GND (Low).
The gate of the pMOS transistor TP2 is connected to VDD (High).
The gate of the nMOS transistor TN2 is connected to the S2 line.
(2) When the Signal Level of the Input Data is Low.
The gate of the pMOS transistor TP1 is connected to VDD (High).
The gate of the nMOS transistor TN1 is connected to the S1 line.
The gate of the pMOS transistor TP2 is connected to the S2 line.
The gate of the nMOS transistor TN2 is connected to GND (Low).
Thus, complementary output signals S1 and S2 are obtained.
When the signal level of the input data inputted to the control circuit 141 changes from the Low level to the High level, the output signal S1 outputted from the driver circuit 142 also changes its signal level from the Low level to the High level. The pMOS transistor TP1 turns off when the source-gate voltage thereof equals the threshold voltage VTP (negative value) of the pMOS transistor TP1. Here, since a source of the pMOS transistor TP1 is fixed at the power source voltage VDD, the gate voltage of the pMOS transistor TP1 is VDD−|VTP|. This voltage is a High level voltage of the output signal S1 (See FIG. 13(b)).
Further, when the input data mentioned above is changed as in the foregoing case, the output signal S2 changes its signal level from the High level to the Low level. Here, the nMOS transistor TN2 turns off when the source-gate voltage thereof equals the threshold voltage Vtn. At this point, since the source of the nMOS transistor TN2 is fixed at the ground potential GND, the gate voltage of the nMOS transistor is the threshold voltage Vtn. This voltage is a Low level voltage of the output signal S2 (See FIG. 13(b)).
When the signal level of the input data is Low, a similar operation causes the voltage of the output signal S1 to become the threshold voltage Vtn which is a Low level voltage of the output signal S1. Meanwhile, the voltage of the output signal S2 becomes VDD−|Vtp| which is a High level voltage of the output signal S2.
FIG. 14(a) illustrates output signals from driver circuits 125 and 126 in the reduced-amplitude bus driving system illustrated in FIG. 10. FIG. 14(b) illustrates output signals from a conventional inverter driving circuit.
Amplitudes of the output signals from the driving circuits 125 and 126 are VDD−|Vtp|−Vtn, as illustrated in FIG. 14(a). In order to ensure a sufficient performance, a minimum amplitude is set at no less than 0.2V, in the driver circuits 125 and 126. On the other hand, as illustrated in FIG. 14(b), the output signals from the conventional inverter driver circuit swings from the ground potential GND to the power source voltage VDD. A power consumption ratio of the driver circuits 125 and 126 with respect to the conventional inverter driver circuit is proportional to the amplitudes, and the ratio is therefore expressed as: (VDD−|Vtp|−Vtn)×2/VDD. Accordingly, the foregoing power consumption ratio becomes 27%, when: VDD=1.5V, |Vtp|=0.65V, and Vtn=0.65V. Thus, it is possible to remarkably reduce power consumption.
However, the reduced-amplitude bus driving system of FIG. 10 is hardly used in LSI's. This is because the Vth is influenced by variations in the production process and temperature changes, as described below.
FIG. 15 illustrates how a signal amplitude and power consumption are influenced by the changes in the threshold voltage Vth in the reduced-amplitude bus driving system of FIG. 10, the changes being caused by variations in the production process and temperature changes. FIG. 15 illustrates a case where the threshold voltage Vth changes by ±0.1V due to variations in the production process, and changes by ±0.1V due to temperature changes within a range of ±40° C. than the normal temperature.
When the minimum amplitude for guaranteeing sufficient performance is 0.2V, it is necessary that: Vtn=|Vtp|=0.65V or less. In this case, the power consumption ratio of the driving circuits 125 and 126 with respect to the conventional inverter driving circuit is 0.27 as described before. This allows the most remarkable power consumption reduction. Further, in consideration of changes in the threshold voltage Vth, a targeted value of the process needs to be: Vtn(center value)=|Vtp| (center value)=0.45V. In this case, the amplitude is 0.6V, and the power consumption ratio is 0.8. However, Vtn=|Vtp|=0.25V, if variations in the production process and temperature changes cause the threshold voltage Vth to be minimized. As such, the amplitudes become 1.0V and the power consumption ratio becomes 1.35. This causes a reverse effect, thereby increasing the power consumption in the reduced-amplitude bus driving system.
As described, with the conventional reduced-amplitude bus driving system, the amplitudes of the output signals are dependent on changes in the threshold voltage Vth; i.e., dependent on variations in the production process and temperature changes. Accordingly, it is difficult to optimize both power consumption and operational margin, which vary according to the changes in threshold voltage Vth.